MOST® Connectivity IPs
NS V3
NS V2
NS V1
oPHY
ePHY
MediaLB
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MOST150
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MOST25

MOST25 Interface Design IP

"From a market size of 10 million nodes sold in total, ..."

SMSC offers licenses to its own design implementations of a MOST25 Interface. They enable a Licensee to implement SMSC's design of a MOST interface into his integrated circuits -subject to the limits of the semiconductor processing. A MOST Cooperation membership is mandatory.

Due to its technical nature, the usual approach of packet switched networks like USB and Ethernet, to integrate a MAC and leave the PHY as a separate chip does not make sense with MOST. MOST is a synchronous network with a permanent data communication and demanding clock jitter and timing requirements. In addition to the standard PHY functions, a routing engine (realized with a RISC controller) is required in the PHY of each node that drives the low level data stream around the ring. The MAC functions are simple and are mainly realized as firmware modules that run on the same engine.  The separation of a MAC therefore does not save cost. MOST Interface Design IP integration is at least a partial PHY integration.

Two options remain for design IP integration:

  1. Full MOST25 Interface Design IP Integration: The mixed-signal MOST network interface is fully integrated on Licensee’s product. It is assumed that the design would need to be ported to customer’s chosen semiconductor process technology by SMSC.
  2. Digital MOST25 Interface Design IP Integration: Only the digital parts of the MOST network interface are integrated on Licensee’s product. The analog (analogy) portions, mainly clock and data recovery are realized as a separate IC.

The suitability of either option must be assessed on a case-by-case basis. SMSC offers a royalty-bearing license and supports licensees on a fee basis to ensure interoperability with SMSC's existing implementations.

Updated Monday, 25 July 2011
Permalink: http://www.smsc-ais.com/MOST_Connectivity_IP_MOST25_Interface_Design_IP