Description

The MediaLB SRAM interface provides data ports for:

• Control data
• Asynchronous data
• Synchronous data

The transfer buffer for different data types is part of the design. By configuring control registers, the functionality of the interface can be defined. Control registers and data buffers are accessible via the SRAM interface port.

The design of the MediaLB SRAM interface is intended for implementation in a XILINX® Spartan® II XC2S200 FPGA. With adaptations, it can be easily ported to other types of FPGAs.