Features

• Implements MediaLB link layer requirements
• Supports MediaLB 3-Pin interfaces
• Selectable MediaLB clock rate: 256Fs or 512Fs
• Implements MediaLB lock detection
• 8-bit SRAM interface
• Supports control, asynchronous and synchronous data
• Supports single or double buffers for control and asynchronous Rx/Tx packet transfer
• Includes double buffers for synchronous Rx/Tx data transfer
• Adjustable sizes for all buffers
• Flexible interrupt rate for synchronous data transfer
• Supports Big-Endian and Little-Endian data format
• Provides hardware loop-back test mode