MediaLB SRAM Interface is a complete MediaLB device implementation for FPGAs. It is provided as VHDL source code to develop a MediaLB SRAM converter chip and to connect a standard application controller via an SRAM interface to MediaLB 3-Pin. The VHDL code is implemented and tested for a specific FPGA, but can be easily ported to other types of FPGAs.

The MediaLB SRAM interface is a complete VHDL design for an FPGA. It incorporates all state machines necessary for transferring control, asynchronous and synchronous data on MediaLB 3-Pin. It serves as an interface between the MediaLB port of an INIC and an 8-bit SRAM port of a standard microcontroller.