Desription

The MediaLB Device Core provides a MediaLB port for all MediaLB-relevant signals to access MediaLB data bytes and protocol information as well as signals required for controlling MediaLB Device Core functionality. The functionality of the application depends on the requirements of the device to be implemented. It can handle a single MediaLB ChannelAddress or multiple ChannelAddresses. It is also suitable for a single data type or all kinds of data types like control, asynchronous, synchronous and isochronous data.

The MediaLB application can work as an interface to various back-end interfaces e.g., AMBA, PCI, DMA or an I/O register interface.

In addition to the available VHDL source code of the core, a VHDL MediaLB host module is included. This module features an I/O interface, and can be used as a MediaLB controller and generic MediaLB pattern generator for device simulation and design verification.