MediaLB Device Implementations
Different grades of MediaLB device implementations are
available as VHDL™ source code to support your development:
- MediaLB Device Core implements the lower layers of
the MediaLB interface. The device core performs
serial to parallel and parallel to serial data transformation of MediaLB 3-Pin data.
- MediaLB SRAM Interface is a complete MediaLB device
implementation for FPGAs. It is provided as VHDL
source code to develop a MediaLB SRAM converter
chip and to connect a standard application controller
via a SRAM interface to MediaLB 3-Pin. The VHDL
code is implemented and tested for a specific FPGA,
but can be easily ported to other types of FPGAs.
- MediaLB Device Interface Macro OS62420 represents
Intellectual Property (IP) used to integrate a fully functional MediaLB device into a system-on-chip (SoC).
The IP is provided as VHDL source code and supports
MediaLB 3-Pin as well as MediaLB 6-Pin interfaces. It
also features an Advanced Microcontroller Bus Architecture (AMBA®)-compliant user interface for integration into the system architecture.
NS V1
oPHY
ePHY
DTCP
MOST150
MOST50
MOST25
MediaLB Physical Layer Implementation
NS V1
oPHY
ePHY
DTCP
MOST150
MOST50
MOST25
Complete MediaLB Device Implementation
NS V1
oPHY
ePHY
DTCP
MOST150
MOST50
MOST25
VHDL Block for SOCs
For the MediaLB Device Interface Macro License Agreement please contact us: