Description
A MediaLB system consists of several MediaLB devices
and one MediaLB controller (typically an INIC chip). The
INIC serves as a transceiver for the MOST network and as
a controller for MediaLB, which assures synchronization
to the MOST network.
MediaLB Characteristics
- The MediaLB controller functions as the timing master
and generates the clock signal and MediaLB frames
- MediaLB is synchronized to the MOST network
- MediaLB includes the definition of a single-ended 3-Pin and a differential 6-Pin physical layer interface
- MediaLB consists of the following signals:
- MLBCLK - provides timing for the entire MediaLB system
- MLBSIG - carries signaling information
- MLBDAT - carries data
- MLBCLK supports multiple data rates:
- MediaLB 3-Pin: 256Fs, 512Fs, 1024Fs
- MediaLB 6-Pin: 2048Fs, 3072Fs, 4096Fs, 6144Fs, 8192Fs
- Frames are divided in 4 byte blocks (quadlets)
- The unique FRAMESYNC pattern transmitted by the
MediaLB controller defines the frame boundary
(between each MediaLB frame)
MediaLB 3-Pin Data Structure
